1) 7,886,102 02/08/2011 Apparatus for determining compatibility between devices (Intel)
2) 7,836,165 11/16/2010 Direct memory access (DMA) transfer of network interface statistics (Intel)
3) 7,831,974 11/09/2010 Method and apparatus for serialized mutual exclusion (Intel)
4) 7,761,666 07/20/2010 Temporally relevant data placement (Intel)
5) 7,573,879 08/11/2009 Method and apparatus for generating a header in a communication network (Intel)
6) 7,464,212 12/09/2008 Method and apparatus for determining compatibility between devices (Intel)
7) 7,447,233 11/04/2008 Packet aggregation protocol for advanced switching (Intel)
8) 7,313,140 11/25/2007 Method and apparatus to assemble data segments into full packets for efficient packet-based classification (Intel)
9) 7,246,205 06/17/2007 Software controlled dynamic push cache (Intel)
10) 7,191,433 03/13/2007 Compiler for computer programming language including instruction statements for handling network packets (Intel)
11) 7,171,486 01/30/2007 Reassembly of a transmission control protocol (TCP) data stream from payloads of TCP segments of a bidirectional TCP connection (Intel)
12) 7,113,985 09/26/2006 Allocating singles and bursts from a freelist (Intel)
13) 7,103,821 09/05/2006 Method and apparatus for improving network router line rate performance by an improved system for error checking (Intel)
14) 7,039,054 05/02/2006 Method and apparatus for header splitting/splicing and automating recovery of transmit resources on a per-transmit granularity (Intel)
15) 6,996,639 02/07/2006 Configurably prefetching head-of-queue from ring buffers (Intel)
16) 6,859,841 02/22/2005 Programmable system for processing a partitioned network infrastructure (I)
17) 6,701,338 03/02/2004 Cumulative status of arithmetic operations (Intel)
18) 6,625,689 09/23/2003 Multiple consumer-multiple producer rings (Intel)
19) 6,421,730 07/16/2002 Programmable system for processing a partitioned network infrastructure (Intel)
20) 6,401,117 06/04/2002 Platform permitting execution of multiple network infrastructure applications (Intel)
21) 6,157,955 12/05/2000 Packet processing system including a policy engine having a classification unit (NetBoost/Intel)
22) 5,956,756 09/21/1999 Virtual address to physical address translation of pages with unknown and variable sizes (Sun)
23) 5,892,957 04/06/1999 Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system (Sun)
24) 5,822,381 10/13/1998 Distributed global clock system (Silicon Graphics)
25) 5,727,219 03/10/1998 Virtual input/output processor utilizing an interrupt handler (Sun)
26) 5,692,197 11/25/1997 Method and apparatus for reducing power consumption in a computer network without sacrificing performance (Sun)
27) 5,689,713 11/18/1997 Method and apparatus for interrupt communication in a packet-switched computer system (Sun)
28) 5,657,472 08/12/1997 Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor (Sun)
29) 5,572,734 11/05/1996 Method and apparatus for locking arbitration on a remote bus (Sun)
30) 5,560,019 09/24/1996 Method and apparatus for handling interrupts in a multiprocessor computer system (Sun)
31) 5,479,627 12/26/1995 Virtual address to physical address translation cache that supports multiple page sizes (Sun)
32) 5,367,695 11/22/1994 Bus-to-bus interface for preventing data incoherence in a multiple processor computer system (Sun)
33) 5,287,503 02/15/1994 System having control registers coupled to a bus whereby addresses on the bus select a control register and a function to be performed on the control register (Sun)
34) 4,951,248 08/21/1990 Self configuring memory system (Sun) (Added as an inventor post-issue)
